-- Declaration of memory type and shared variable.
    type memoryByteArray is array(0 to 1023) of std_logic_vector(7 downto 0);
    shared variable memoryBlock : memoryByteArray:=(others =>(others=> '0'));


-- Process for read and writr
   PortA: process(portA_clk)    
          variable address : integer range 0 to 1023 := 0;
        begin
           if rising_edge(PortA_clk) then
             address := to_integer(unsigned(portA_addr));
             if(portA_writeEnable='1') then
               memoryBlock(address) := PortA_dataIn;
             end if;
             portA_dataOut <= memoryBlock(address);
          end if;
    end process PortA;
        
    PortB: process(portB_clk)
           variable address: integer range 0 to 1023:=0;
         begin
            if rising_edge(PortB_clk) then
                address := to_integer(unsigned(portB_addr));
                if(portB_writeEnable='1') then
                  memoryBlock(address) := PortB_dataIn;
                end if;
                portB_dataOut <= memoryBlock(address);
            end if;
     end process PortB;