component register8 
    Port ( clock : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR (7 downto 0);
           data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;

signal Channel_1_registered_data : std_logic_vector(7 downto 0);
signal mux_data_selected : STD_LOGIC_VECTOR (7 downto 0); 

regCh1: register8 port map (
  clock => clock,
  reset => reset,
  enable => Channel_1_enable,
  data_in => Channel_1_data,
  data_out => Channel_1_registered_data
);

with selector select
  mux_data_selected <= 
    Channel_1_registered_data when '0',
    Channel_2_registered_data when '1',
    (others => '-') when others;

--Alternatively
mux_data_selected <= Channel_1_registered_data when (selector = '0') else Channel_2_registered_data;

data_out <= mux_data_selected when rising_edge(clock);


----------------------------------------------
-- For Testbench

component LED_manager
    Port ( Channel_1_data : in STD_LOGIC_VECTOR (7 downto 0);
           Channel_2_data : in STD_LOGIC_VECTOR (7 downto 0);
           Channel_1_enable : in STD_LOGIC;
           Channel_2_enable : in STD_LOGIC;
           selector : in STD_LOGIC;
           clock : in STD_LOGIC;
           reset : in STD_LOGIC;
           data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component LED_manager;


uut: LED_manager Port Map ( 
           Channel_1_data   => Channel_1_data  , 
           Channel_2_data   => Channel_2_data  , 
           Channel_1_enable => Channel_1_enable, 
           Channel_2_enable => Channel_2_enable, 
           selector         => selector        , 
           clock            => clock           , 
           reset            => reset           , 
           data_out         => data_out        );
		   
		   

signal Channel_1_data  : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal Channel_2_data  : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal Channel_1_enable: STD_LOGIC := '0';
signal Channel_2_enable: STD_LOGIC := '0';
signal selector        : STD_LOGIC := '0';
signal clock           : STD_LOGIC := '0';
signal reset           : STD_LOGIC := '0';
signal data_out        : STD_LOGIC_VECTOR (7 downto 0);


   reset <= '1', '0' after clock_period*10;
   clock <= not clock after 5 ns;
   selector <= '0', '1' after clock_period*20, '0' after clock_period*50, '1' after clock_period*100;
   
   Channel_1_data <= Channel_1_data + X"03" after clock_period * 2;
   Channel_2_data <= Channel_2_data + X"04" after clock_period * 3;
   Channel_1_enable <= '1';
   Channel_2_enable <= '1';








