 ****** UART_LED_full_tb ******
-- Compoenet declaration (step 3-3-2)
       component uart_led is
            Generic (CLOCK_RATE : integer := 50_000_000;
                     BAUD_RATE  : integer :=    115_200
                    );
           Port ( clk_pin       : in  STD_LOGIC;
                  rst_pin       : in  STD_LOGIC;
                  rxd_pin       : in  STD_LOGIC;
                  sel_pin       : in  STD_LOGIC;
                  led_pins      : out STD_LOGIC_VECTOR (7 downto 0)
                );
       end component uart_led;

-- Component instatiation
            UUT: uart_led
             generic map (CLOCK_RATE => CLOCK_RATE,
                          BAUD_RATE  =>    BAUD_RATE )
             Port map ( clk_pin => clk_rx,
                   rst_pin     => rst_clk_rx,
                   rxd_pin     => rxd_clk_rx,
                   sel_pin     => gnd(0),
                   led_pins    => rx_data
                 );
        
-- Signal declaration
       signal gnd : std_logic_vector(7 downto 0) := (others=> '0');   
              
       signal new_data_present : std_logic := 'U';
       signal last_datum : std_logic_vector(7 downto 0) := (others => 'U');		

-- response checker (3.4)
