
process (clk_dst, rst_in)
   variable rst_meta: std_logic:= 'U';
begin
      if rst_in = '1' then
         rst_meta := '1';
         rst_out  <= '1';
      elsif (clk_dst'event and clk_dst= '1') then
          rst_out  <= rst_meta;
          rst_meta := '0';
      end if;
end process;


-- Using signals
architecture Behav_signals of reset_bridge is
	signal rst_meta: std_logic;
begin

process (clk_dst, rst_in)
begin
      if rst_in = '1' then
         rst_meta <= '1';
         rst_out  <= '1';
      elsif (clk_dst'event and clk_dst= '1') then
          rst_out  <= rst_meta;
          rst_meta <= '0';
      end if;
end process;
				
end Behav_signals;