Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta	FALSE	build_version	2552052
date_generated	Thu Aug 22 14:47:10 2019	os_platform	WIN64
product_version	Vivado v2019.1 (64-bit)	project_id	96d90d29537e4f17843dcba61fad768f
project_iteration	5	random_id	4e1236f89dbe59349eb2c24e5c011796
registration_id	1_2_4_3	route_design	TRUE
target_device	xcku040	target_family	kintexu
target_package	ffva1156	target_speed	-2
tool_flow	Vivado

user_environment
cpu_name	Intel(R) Xeon(R) E-2176M CPU @ 2.70GHz	cpu_speed	2712 MHz
os_name	Windows Server 2016 or Windows 10	os_release	major release (build 9200)
system_ram	34.000 GB	total_processors	1

vivado_usage

gui_handlers
basedialog_cancel=1	basedialog_ok=15	basedialog_yes=1	exprunmenu_change_run_settings=4
exprunmenu_make_active=1	expruntreepanel_exp_run_tree_table=9	flownavigatortreepanel_flow_navigator_tree=2	gettingstartedview_open_project=1
mainmenumgr_file=2	mainmenumgr_project=1	pacommandnames_close_project=1	pacommandnames_run_bitgen=1
programoptionsdialog_report_strategy=2	programoptionspanelimpl_strategy=4	touchpointsurveydialog_remind_me_later=1

java_command_handlers
addsources=3	autoconnecttarget=2	closedesign=2	closeproject=9
launchopentarget=1	launchprogramfpga=3	newproject=1	openhardwaremanager=3
openproject=7	projectsettingscmdhandler=1	reportutilization=1	runbitgen=6
runimplementation=2	runsynthesis=1	settopnode=1	simulationclose=1
simulationrestart=1	simulationrun=1	simulationrunfortime=1	toolssettings=1
viewtaskimplementation=1

other_data
guimode=10

project_data
constraintsetcount=1	core_container=false	currentimplrun=impl_1	currentsynthesisrun=synth_1
default_library=xil_defaultlib	designmode=RTL	export_simulation_activehdl=0	export_simulation_ies=0
export_simulation_modelsim=0	export_simulation_questa=0	export_simulation_riviera=0	export_simulation_vcs=0
export_simulation_xsim=0	implstrategy=Vivado Implementation Defaults	launch_simulation_activehdl=0	launch_simulation_ies=0
launch_simulation_modelsim=0	launch_simulation_questa=0	launch_simulation_riviera=0	launch_simulation_vcs=0
launch_simulation_xsim=1	simulator_language=Mixed	srcsetcount=6	synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL	target_simulator=XSim	totalimplruns=1	totalsynthesisruns=1

unisim_transformation

post_unisim_transformation
bufgce=1	diffinbuf=1	fdre=38	fdse=6
gnd=3	ibufctrl=3	inbuf=2	lut1=3
lut2=13	lut3=6	lut4=9	lut5=9
lut6=14	obuf=8	vcc=6

pre_unisim_transformation
bufgce=1	fdre=38	fdse=6	gnd=3
ibuf=2	ibufds=1	lut1=3	lut2=13
lut3=6	lut4=9	lut5=9	lut6=14
obuf=8	vcc=6

synthesis

command_line_options
-assert=default::[not_specified]	-bufg=default::12	-cascade_dsp=default::auto	-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto	-directive=default::default	-fanout_limit=default::10000	-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto	-gated_clock_conversion=default::off	-generic=default::[not_specified]	-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]	-max_bram=default::-1	-max_bram_cascade_height=default::-1	-max_dsp=default::-1
-max_uram=default::-1	-max_uram_cascade_height=default::-1	-mode=default::default	-name=default::[not_specified]
-no_lc=default::[not_specified]	-no_srlextract=default::[not_specified]	-no_timing_driven=default::[not_specified]	-part=xcku040-ffva1156-2-e
-resource_sharing=default::auto	-retiming=default::[not_specified]	-rtl=default::[not_specified]	-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]	-seu_protect=default::none	-sfcu=default::[not_specified]	-shreg_min_size=default::3
-top=uart_led	-verilog_define=default::[not_specified]

usage
elapsed=00:00:28s	hls_ip=0	memory_gain=1017.824MB	memory_peak=1397.676MB

xsim

command_line_options
-sim_mode=default::behavioral	-sim_type=default::